1 HCS154MS radiation hardened 4 to 16 line decoder/demultiplexer HCS154MS the intersil HCS154MS is a radiation hardened 4 to 16 line decoder/demultiplexer wi th two enable inputs. a high on either enable input forces the output to a high state. the demultiplexing func tion is performed by using the four input lines a0 to a3 to select the desired output states. the HCS154MS utilizes advanc ed cmos/sos technology to achieve high-speed operation. this device is a member of radiation hardened, high-speed, cmos/sos logic family. the HCS154MS is supplied in a 24 lead ceramic flatpack (k suffix) or a sbdip package (d suffix). features ? 3 micron radiation hardened sos cmos ? total dose 200k rad (si) ? sep effective let no upsets: >100 mev-cm 2 /mg ? single event upset (seu) immunity < 2 x 10 -9 errors/bit-day (typ) ? dose rate survivability: >1 x 10 12 rads (si)/s ? dose rate upset >10 10 rad(si)/s 20ns pulse ? cosmic ray upset immunity < 2 x 10 -9 errors/gate day (typ) ? latch-up free under any conditions ? military temperature range: -55 o c to +125 o c ? significant power reduction compared to lsttl ics ? dc operating voltage range: 4.5v to 5.5v ? input logic levels - vil = 30% of vcc max - vih = 70% of vcc min ? input current levels ii 5a at vol, voh pin configurations 24 lead ceramic dual-in-line metal seal package (sbdip) mil-std-1835 cdip2-t24 top view 24 lead ceramic metal seal flatpack package (flatpack) mil-std-1835 cdfp4-f24 top view gnd vcc y 0 y 1 y 2 y 3 y 4 y 5 y 6 y 7 y 8 y 9 y 10 y 11 y 12 y 13 y 14 y 15 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 19 20 21 22 23 24 15 14 13 a0 a1 a2 a3 e 1 e 2 24 23 22 21 20 19 18 17 16 15 14 13 2 3 4 5 6 7 8 9 10 11 12 1 gnd y 0 y 1 y 2 y 3 y 4 y 5 y 6 y 7 y 8 y 9 y 10 vcc y 11 y 12 y 13 y 14 y 15 a0 a1 a2 a3 e 1 e 2 ordering information ordering number internal mkt. number part marking temp. range (c) screening level package pkg. dwg. # 5962r9572901vjc hcs154dmsr q 5962r95 72901vjc -55 o c to +125 o c intersil class s equivalent 24 ld sbdip d24.6 5962r9572901vxc hcs154kmsr q 5962r95 72901vxc -55 o c to +125 o c intersil class s equivalent 24 ld ceramic flatpack k24.a caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 1995, 2011. all rights reserved all other trademarks mentioned are the property of their respective owners. january 6, 2011 fn2479.3
2 fn2479.3 january 6, 2011 functional diagram table 1. truth table inputs outputs e 1e 2 a3a2a1a0y 0y 1y 2y 3y 4y 5y 6y 7y 8y 9y 10 y 11 y 12 y 13 y 14 y 15 l llllll hhhhhhhhhhhhhhh l l lllhhlhhhhhhhhhhhhhh l l llhlhhlhhhhhhhhhhhhh l l llhhhhhlhhhhhhhhhhhh l l lhllhhhhlhhhhhhhhhhh l l lhlhhhhhhlhhhhhhhhhh l l lhhlhhhhhhlhhhhhhhhh l l lhhhhhhhhhhlhhhhhhhh l lhlllhhhhhhhhlhhhhhhh l lhllhhhhhhhhhhlhhhhhh l lhlhlhhhhhhhhhhlhhhhh l lhlhhhhhhhhhhhhhlhhhh l lhhllhhhhhhhhhhhhlhhh l lhhlhhhhhhhhhhhhhhlhh l lhhhlhhhhhhhhhhhhhhlh l l hhhh hhhhhhhhhhhhhhhl lhxxxxhhhhhhhhhhhhhhhh hlxxxxhhhhhhhhhhhhhhhh hhxxxxhhhhhhhhhhhhhhhh note: h = high level, l = low level, x = immaterial HCS154MS
3 fn2479.3 january 6, 2011 absolute maximum rating s reliability information supply voltage. . . . . . . . . . . . . . . . . . . . . . -0.5v to +7.0v input voltage range, all inputs . . . . . . . -0.5v to vcc +0.5v dc input current, any one input . . . . . . . . . . . . . . . . . . . . . 10ma dc drain current, any one output . . . . . . . . . . . . . . . . . . . . 25ma (all voltage reference to the vss terminal) storage temperature range (tstg) . . . . . . -65c to +150c lead temperature (soldering 10sec) . . . . . . . . . . . +265c junction temperature (tj) . . . . . . . . . . . . . . . . . . . +175c esd classification. . . . . . . . . . . . . . . . . . . . . . . . . . class 1 thermal resistance ja jc sbdip package . . . . . . . . . . . . . . 63c/w 23c/w ceramic flatpack package . . . . . . . 87c/w 23c/w maximum package power dissipation at +125 o c ambient sbdip package . . . . . . . . . . . . . . . . . . . . . . . . . . 0.79w ceramic flatpack package . . . . . . . . . . . . . . . . . . . 0.57w if device power exceeds pack age dissipation capability, provide heat sinking or derate linearly at the following rate: sbdip package . . . . . . . . . . . . . . . . . . . . . . 15.9mw/c ceramic flatpack package . . . . . . . . . . . . . . . 11.5mw/c operating conditions supply voltage . . . . . . . . . . . . . . . . . . . . . +4.5v to +5.5v input rise and fall times at 4. 5v vcc (tr, tf) . . . . . 100ns maxoperating temperature range (t a ) . . . -55c to +125c input low voltage (vil) . . . . . . . . . . . . 0.0v to 30% of vcc input high voltage (vih) . . . . . . . . . . . . 70% of vcc to vcc caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. dc electrical specifications symbol parameters conditions (note 1) group a subgroups temperature limits units min max icc quiescent current vcc = 5.5v, vin = vcc or gnd 1 +25c - 40 a 2, 3 +125c, -55c - 750 a iol output current (sink) vcc = 4.5v, vih = 4.5v, vout = 0.4v, vil = 0v 1 +25c 4.8 - ma 2, 3 +125c, -55c 4.0 - ma ioh output current (source) vcc = 4.5v, vih = 4.5v, vout = vcc -0.4v, vil = 0v 1 +25c -4.8 - ma 2, 3 +125c, -55c -4.0 - ma vol output voltage low vcc = 4.5v, vih = 3.15v, iol = 50 a, vil = 1.35v 1, 2, 3 +25c, +125c, -55c - 0.1 v vcc = 5.5v, vih = 3.85v, iol = 50 a, vil = 1.65v 1, 2, 3 +25c, +125c, -55c - 0.1 v voh output voltage high vcc = 4.5v, vih = 3.15v, ioh = -50 a, vil = 1.35v 1, 2, 3 +25c, +125c, -55c vcc -0.1 -v vcc = 5.5v, vih = 3.85v, ioh = -50 a, vil = 1.65v 1, 2, 3 +25c, +125c, -55c vcc -0.1 -v iin input leakage current vcc = 5.5v, vin = vcc or gnd 1 +25c - 0.5 a 2, 3 +125c, -55c - 5.0 a fn noise immunity functional test vcc = 4.5v, vih = 0.70(vcc), (note 2) vil = 0.30(vcc) 7, 8a, 8b +25c, +125c, -55c - - - notes: 1. all voltages refere nce to device gnd. 2. for functional tests, vo 4.0v is recognized as a logic ?1?, and vo 0.5v is recognized as a logic ?0?. HCS154MS
4 fn2479.3 january 6, 2011 ac electrical specifications symbol parameter conditions (notes 3, 4) group a subgroups temperature limits units min max tplh address to output vcc = 4.5v 9 +25c 2 29 ns 10, 11 +125c, -55c 2 34 ns tphl vcc = 4.5v 9 +25c 2 27 ns 10, 11 +125c, -55c 2 31 ns tplh tphl enable to output vcc = 4.5v 9 +25c 2 27 ns 10, 11 +125c, -55c 2 27 ns notes: 3. all voltages referenced to device gnd. 4. ac measurements assume rl = 500 , cl = 50pf, input tr = tf = 3ns, vil = gnd, vih = vcc. electrical specifications the following parameters are controlled via design or process pa rameters. min and max limits are guaranteed but not directly test ed. these parameters are characterized upon initial design release and upon design ch anges which affect these characteristics. symbol parameter conditions notes temperature limits units min max cpd capacitance power dissipation vcc = 5.0v, f = 1mhz 1 +25c - 66 pf 1 +125c, -55c - 74 pf cin input capacitance vcc = 5.0v, f = 1mhz 1 +25c - 10 pf 1 +125c - 10 pf tthl ttlh output transition time vcc = 4.5v 1 +25c - 15 ns 1 +125c - 22 ns dc post radiation electrical performance characteristics symbol parameters conditions (notes 5, 6) temperature 200k rad limits units min max icc quiescent current vcc = 5.5v, vin = vcc or gnd +25c - 0.75 ma iol output current (sink) vcc = 4.5v, vin = vcc or gnd, vout = 0.4v +25c 4.0 - ma ioh output current (source) vcc = 4.5v, vin = vcc or gnd, vout = vcc -0.4v +25c -4.0 - ma vol output voltage low vcc = 4.5v and 5.5v, vih = 0.70(vcc), vil = 0.30(vcc), iol = 50 a +25c - 0.1 v voh output voltage high vcc = 4.5v or 5.5v, vih = 0.70(vcc), vil = 0.30(vcc), ioh = -50 a +25c vcc -0.1 -v iin input leakage current vcc = 5.5v, vin = vcc or gnd +25c - 5a fn noise immunity functional test vcc = 4.5v, vih = 0.70(vcc), vil = 0.30(vcc), (note 7) +25c --- tplh address to output vcc = 4.5v +25c 2 34 ns tphl vcc = 4.5v +25c 2 31 ns tplh tphl enable to output vcc = 4.5v +25c 2 27 ns notes: 5. all voltages referenced to device gnd. 6. ac measurements assume rl = 500 , cl = 50pf, input tr = tf = 3ns, vil = gnd, vih = vcc. 7. for functional tests, vo 4.0v is recognized as a logic ?1?, and vo 0.5v is recognized as a logic ?0?. HCS154MS
5 fn2479.3 january 6, 2011 table 5. burn-in and operating life test, delta parameters (+25c) parameter group b subgroup delta limit icc 5 12 a iol/ioh 5 -15% of 0 hour table 6. applicable subgroups conformance groups method group a subgroups read and record initial test (preburn-in) 100%/5004 1, 7, 9 icc, iol/h interim test i (postburn-in) 100%/5004 1, 7, 9 icc, iol/h interim test ii (postburn-in) 100%/5004 1, 7, 9 icc, iol/h pda 100%/5004 1, 7, 9, deltas interim test iii (postburn-in) 100%/5004 1, 7, 9 icc, iol/h pda 100%/5004 1, 7, 9, deltas final test 100%/5004 2, 3, 8a, 8b, 10, 11 group a (note 8) sample/5005 1, 2, 3, 7, 8a, 8b, 9, 10, 11 group b subgroup b-5 sample/5005 1, 2, 3, 7, 8a, 8b, 9, 10, 11, deltas subgroups 1, 2, 3, 9, 10, 11 subgroup b-6 sample/5005 1, 7, 9 group d sample/5005 1, 7, 9 note: 8. alternate group a testing in accordance with method 5005 of mil-std-883 may be exercised. table 7. total dose irradiation conformance groups method test read and record pre rad post rad pre rad post rad group e subgroup 2 5005 1, 7, 9 see ?dc post radiation electrical performance characteristics? table on page 4 1, 9 see ?dc post ra diation electrical performance characteristics? table on page 4 (note 9) note: 9. except fn test wh ich will be performed 100% go/no-go. table 8. static and dynamic burn-in test connections open ground 1/2 vcc = 3v 0.5v vcc = 6v 0.5v oscillator 50khz 25khz static burn-in i test conditions (note 10) 1 - 11, 13 - 17 12, 18 - 23 - 24 - - static burn-in ii test connections (note 10) 1 - 11, 13 - 17 12 - 18 - 24 - - dynamic burn-in i test connections (note 11) - 12, 18 - 21 1 - 11, 13 - 17 24 23 22 notes: 10. each pin except vcc and gnd will have a resistor of 10 k 5% for static burn-in. 11. each pin except vcc and gnd will have a resistor of 1k 5% for dynamic burn-in. table 9. irradiation test connections open ground vcc = 5v 0.5v 1 - 11, 13 - 17 12 18 - 24 note: each pin except vcc and gnd will have a resistor of 47k 5% for irradiation testing. gr oup e, subgroup 2, sample size is 4 dice/wafer 0 failures. HCS154MS
6 fn2479.3 january 6, 2011 intersil space level product flow - ?ms? wafer lot acceptance (all lots) method 5007 (includes sem) gamma radiation verification (each wafer) method 1019, 4 samples/wafer, 0 rejects 100% nondestructive bond pull, method 2023 sample - wire bond pull monitor, method 2011 sample - die shear monitor, method 2019 or 2027 100% internal visual inspection, method 2010, condition a 100% temperature cycle, method 1010, condition c, 10 cycles 100% constant acceleration, method 2001, condition per method 5004 100% pind, method 2020, condition a 100% external visual 100% serialization 100% initial electrical test (t0) 100% static burn-in 1, condition a or b, 24 hrs. min., +125c min., method 1015 100% interim electrical test 1 (t1) 100% delta calculation (t0-t1) 100% static burn-in 2, condition a or b, 24 hrs. min., +125c min., method 1015 100% interim electrical test 2 (t2) 100% delta calculation (t0-t2) 100% pda 1, method 5004 (notes 12 and 13) 100% dynamic burn-in, condition d, 240 hrs., +125c or equivalent, method 1015 100% interim electrical test 3 (t3) 100% delta calculation (t0-t3) 100% pda 2, method 5004 (note 13) 100% final electrical test 100% fine/gross leak, method 1014 100% radiographic, method 2012 (note 14) 100% external visual, method 2009 sample - group a, method 5005 (note 15) 100% data package generation (note 16) notes: 12. failures from interim elec trical test 1 and 2 are combined for determining pda 1. 13. failures from subgroup 1, 7, 9 and deltas are used for calculat ing pda. the maximum allowable pda = 5% with no more than 3% of the failures from subgroup 7. 14. radiographic (x-ray) inspection may be performed at any point after serialization as allowed by method 5004. 15. alternate group a testing may be performe d as allowed by mil-std-883, method 5005. 16. data package contents: ? cover sheet (intersil name and/or logo, p.o. number, customer part number, lot da te code, intersil part number, lot num- ber, quantity). ? wafer lot acceptance report (method 5007). includes repr oductions of sem photos with percent of step coverage. ? gamma radiation report. contains cover page, disposition, ra d dose, lot number, test package used, specification numbers, te s t equipment, etc. radiation read and record data on file at intersil. ? x-ray report and film. includes penetrometer measurements. ? screening, electrical, and group a attributes (screening attributes begin after package seal). ? lot serial number sheet (good uni ts serial number and lot number). ? variables data (all delta operations). data is identified by serial number. data head er includes lot number and date of test. ? the certificate of conformance is a part of the shipping invoic e and is not part of the data book. the certificate of confor- mance is signed by an authorized quality representative. HCS154MS
7 fn2479.3 january 6, 2011 ac timing diagrams ac load circuit table 10. ac voltage levels parameter hcs units vcc 4.50 v vih 4.50 v vs 2.25 v vil 0 v gnd 0 v vs input output output tthl 80% 20% 80% 20% vih vil voh vol voh vol tplh tphl vs ttlh dut test cl rl point cl = 50pf rl = 500 HCS154MS
8 intersil products are manufactured, assembled and tested utilizing iso9000 qu ality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, th e reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accura te and reliable. however, no re sponsibility is assumed by inte rsil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which ma y result from its use. no licen se is granted by implication o r otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn2479.3 january 6, 2011 for additional products, see www.intersil.com/product_tree die characteristics die dimensions: 85 x 101 mils 2.16 x 2.57mm metallization: ty pe : a l si metal thickness: 11k ? 1k ? glassivation: ty pe : s i o 2 thickness: 13k ? 2.6k ? worst case current density: 2.0 x 10 5 a/cm 2 bond pad size: 100m x 100m 4 x 4 mils metallization mask layout HCS154MS y 0 (1) y 1 (2) y 2 (3) y 3 (4) y 4 (5) y 5 (6) y 6 (7) y 7 (8) y 8 (9) y 9 (10) (11) y 10 (12) gnd (13) y 11 (14) y 12 (15) y 13 (21) a2 (20) a3 (19) e 2 (18) e 1 (17) y 15 (16) y 14 vcc (24) a0 (23) a1 (22) HCS154MS
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